[IA64] Don't use hard wired privilege level 2 for domain kernel

PV domains now use CPL 1 instead of 2 for CPL 0 emulation

Signed-off-by: Juergen Gross <juergen.gross@fujitsu-siemens.com>

diff --git a/xen/arch/ia64/xen/domain.c b/xen/arch/ia64/xen/domain.c
index 14e529e5bd9370de61b33cc8cd30144d4297c56c..0844bbb97dc387741a5811d1b2f6081f34180bb2 100644 (file)
--- a/xen/arch/ia64/xen/domain.c
+++ b/xen/arch/ia64/xen/domain.c
@@ -838,8 +838,9 @@ int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
        
        if (!d->arch.is_vti) {
                /* domain runs at PL2/3 */
-               uregs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
-               uregs->ar_rsc |= (2 << 2); /* force PL2/3 */
+               uregs->cr_ipsr = vcpu_pl_adjust(uregs->cr_ipsr,
+                                               IA64_PSR_CPL0_BIT);
+               uregs->ar_rsc = vcpu_pl_adjust(uregs->ar_rsc, 2);
        }
 
        for (i = 0; i < IA64_NUM_DBG_REGS; i++) {

diff --git a/xen/arch/ia64/xen/faults.c b/xen/arch/ia64/xen/faults.c
index 63be84df2f2fbd84bcb7b7bee5c45f588dfee106..2c657a82e05e06b60ca96ecc77beff7fc3d6a59f 100644 (file)
--- a/xen/arch/ia64/xen/faults.c
+++ b/xen/arch/ia64/xen/faults.c
@@ -38,10 +38,9 @@ extern void die_if_kernel(char *str, struct pt_regs *regs, long err);
 extern int ia64_hyperprivop(unsigned long, REGS *);
 extern IA64FAULT ia64_hypercall(struct pt_regs *regs);
 
-#define IA64_PSR_CPL1  (__IA64_UL(1) << IA64_PSR_CPL1_BIT)
 // note IA64_PSR_PK removed from following, why is this necessary?
 #define        DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
-                       IA64_PSR_DT | IA64_PSR_RT | IA64_PSR_CPL1 | \
+                       IA64_PSR_DT | IA64_PSR_RT | \
                        IA64_PSR_IT | IA64_PSR_BN)
 
 #define        DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL | IA64_PSR_DFH |    \
@@ -92,6 +91,7 @@ static void reflect_interruption(unsigned long isr, struct pt_regs *regs,
 
        regs->cr_iip = ((unsigned long)PSCBX(v, iva) + vector) & ~0xffUL;
        regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
+       regs->cr_ipsr = vcpu_pl_adjust(regs->cr_ipsr, IA64_PSR_CPL0_BIT);
        if (PSCB(v, dcr) & IA64_DCR_BE)
                regs->cr_ipsr |= IA64_PSR_BE;
 
@@ -137,6 +137,7 @@ void reflect_event(void)
 
        regs->cr_iip = v->arch.event_callback_ip;
        regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
+       regs->cr_ipsr = vcpu_pl_adjust(regs->cr_ipsr, IA64_PSR_CPL0_BIT);
        if (PSCB(v, dcr) & IA64_DCR_BE)
                regs->cr_ipsr |= IA64_PSR_BE;
 
@@ -236,6 +237,8 @@ void ia64_do_page_fault(unsigned long address, unsigned long isr,
                    ((unsigned long)PSCBX(current, iva) + fault) & ~0xffUL;
                regs->cr_ipsr =
                    (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
+               regs->cr_ipsr = vcpu_pl_adjust(regs->cr_ipsr,
+                                              IA64_PSR_CPL0_BIT);
 
                if (PSCB(current, hpsr_dfh))
                        regs->cr_ipsr |= IA64_PSR_DFH;  
@@ -503,7 +506,7 @@ ia64_handle_break(unsigned long ifa, struct pt_regs *regs, unsigned long isr,
 
        /* FIXME: don't hardcode constant */
        if ((iim == 0x80001 || iim == 0x80002)
-           && ia64_get_cpl(regs->cr_ipsr) == 2) {
+           && ia64_get_cpl(regs->cr_ipsr) == CONFIG_CPL0_EMUL) {
                do_ssc(vcpu_get_gr(current, 36), regs);
        }
 #ifdef CRASH_DEBUG
@@ -513,7 +516,8 @@ ia64_handle_break(unsigned long ifa, struct pt_regs *regs, unsigned long isr,
                debugger_trap_fatal(0 /* don't care */ , regs);
        }
 #endif
-       else if (iim == d->arch.breakimm && ia64_get_cpl(regs->cr_ipsr) == 2) {
+       else if (iim == d->arch.breakimm &&
+                ia64_get_cpl(regs->cr_ipsr) == CONFIG_CPL0_EMUL) {
                /* by default, do not continue */
                v->arch.hypercall_continuation = 0;
 
@@ -523,7 +527,7 @@ ia64_handle_break(unsigned long ifa, struct pt_regs *regs, unsigned long isr,
                } else
                        reflect_interruption(isr, regs, vector);
        } else if ((iim - HYPERPRIVOP_START) < HYPERPRIVOP_MAX
-                  && ia64_get_cpl(regs->cr_ipsr) == 2) {
+                  && ia64_get_cpl(regs->cr_ipsr) == CONFIG_CPL0_EMUL) {
                if (ia64_hyperprivop(iim, regs))
                        vcpu_increment_iip(current);
        } else {

diff --git a/xen/arch/ia64/xen/hyperprivop.S b/xen/arch/ia64/xen/hyperprivop.S
index 287e6d3c2be24fb1d45996c51ed5f2f61fd4181b..d70662529eb3a40877162ff40c37e475a15118e4 100644 (file)
--- a/xen/arch/ia64/xen/hyperprivop.S
+++ b/xen/arch/ia64/xen/hyperprivop.S
@@ -18,9 +18,8 @@
 
 
 #define        _PAGE_PPN_MASK  0x0003fffffffff000 //asm/pgtable.h doesn't do assembly
-#define PAGE_PHYS      0x0010000000000761 //__pgprot(__DIRTY_BITS|
-                                          //         _PAGE_PL_2|_PAGE_AR_RWX)
-#define _PAGE_PL_2     (2<<7)
+#define PAGE_PHYS      (0x0010000000000661 | _PAGE_PL_PRIV)
+                       //__pgprot(__DIRTY_BITS|_PAGE_PL_PRIV|_PAGE_AR_RWX)
 
 #if 1   // change to 0 to turn off all fast paths
 # define FAST_HYPERPRIVOPS
@@ -62,7 +61,7 @@
 #define IA64_PSR_CPL0  (__IA64_UL(1) << IA64_PSR_CPL0_BIT)
 // note IA64_PSR_PK removed from following, why is this necessary?
 #define        DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
-                       IA64_PSR_DT | IA64_PSR_RT | IA64_PSR_CPL1 | \
+                       IA64_PSR_DT | IA64_PSR_RT | \
                        IA64_PSR_IT | IA64_PSR_BN)
 
 #define        DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL | IA64_PSR_DFH | \
@@ -249,8 +248,8 @@ ENTRY(hyper_ssm_i)
        mov r29=r30 ;;
        movl r28=DELIVER_PSR_SET;;
        movl r27=~DELIVER_PSR_CLR;;
-       or r29=r29,r28;;
        and r29=r29,r27;;
+       or r29=r29,r28;;
        // set hpsr_dfh to ipsr
        adds r28=XSI_HPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
        ld1 r28=[r28];;
@@ -258,8 +257,7 @@ ENTRY(hyper_ssm_i)
        mov cr.ipsr=r29;;
        // set shared_mem ipsr (from ipsr in r30 with ipsr.ri already set)
        extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
-       cmp.eq p6,p7=3,r29;;
-(p6)   dep r30=-1,r30,IA64_PSR_CPL0_BIT,2
+       cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
 (p7)   dep r30=0,r30,IA64_PSR_CPL0_BIT,2
        ;;
        // FOR SSM_I ONLY, also turn on psr.i and psr.ic
@@ -441,20 +439,18 @@ GLOBAL_ENTRY(fast_tick_reflect)
        st8 [r21]=r16 ;;
        // set cr.ipsr (make sure cpl==2!)
        mov r29=r17 ;;
-       movl r28=DELIVER_PSR_SET;;
-       movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0);;
-       or r29=r29,r28;;
+       movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
+       movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1);;
        and r29=r29,r27;;
+       or r29=r29,r28;;
        mov cr.ipsr=r29;;
        // set shared_mem ipsr (from ipsr in r17 with ipsr.ri already set)
        extr.u r29=r17,IA64_PSR_CPL0_BIT,2;;
-       cmp.eq p6,p7=3,r29;;
-(p6)   dep r17=-1,r17,IA64_PSR_CPL0_BIT,2
+       cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
 (p7)   dep r17=0,r17,IA64_PSR_CPL0_BIT,2
        ;;
        movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
        movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN|IA64_PSR_I|IA64_PSR_IC);;
-       dep r21=-1,r21,IA64_PSR_CPL1_BIT,1 ;;
        or r17=r17,r28;;
        and r17=r17,r27;;
        ld4 r16=[r18];;
@@ -620,10 +616,10 @@ ENTRY(fast_reflect)
        movl r21=THIS_CPU(current_psr_i_addr)
        mov r29=r30 ;;
        ld8 r21=[r21]
-       movl r28=DELIVER_PSR_SET;;
-       movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0);;
-       or r29=r29,r28;;
+       movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
+       movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1);;
        and r29=r29,r27;;
+       or r29=r29,r28;;
        // set hpsr_dfh to ipsr
        adds r28=XSI_HPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
        ld1 r28=[r28];;
@@ -631,8 +627,7 @@ ENTRY(fast_reflect)
        mov cr.ipsr=r29;;
        // set shared_mem ipsr (from ipsr in r30 with ipsr.ri already set)
        extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
-       cmp.eq p6,p7=3,r29;;
-(p6)   dep r30=-1,r30,IA64_PSR_CPL0_BIT,2
+       cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
 (p7)   dep r30=0,r30,IA64_PSR_CPL0_BIT,2
        ;;
        movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
@@ -1112,14 +1107,17 @@ ENTRY(hyper_rfi)
 
 just_do_rfi:
        // r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
-       mov cr.iip=r22;;
+       mov cr.iip=r22
+       extr.u r19=r21,IA64_PSR_CPL0_BIT,2
        adds r20=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
+       cmp.gtu p7,p0=CONFIG_CPL0_EMUL,r19
        ld8 r20=[r20];;
+(p7)   mov r19=CONFIG_CPL0_EMUL
        dep r20=0,r20,38,25;; // ensure ifs has no reserved bits set
        mov cr.ifs=r20 ;;
-       // ipsr.cpl == (vcr.ipsr.cpl == 0) 2 : 3;
+       // ipsr.cpl = max(vcr.ipsr.cpl, IA64_PSR_CPL0_BIT);
        movl r20=THIS_CPU(current_psr_i_addr)
-       dep r21=-1,r21,IA64_PSR_CPL1_BIT,1 ;;
+       dep r21=r19,r21,IA64_PSR_CPL0_BIT,2;;
        // vpsr.i = vcr.ipsr.i; vpsr.ic = vcr.ipsr.ic
        ld8 r20=[r20]
        mov r19=1 
@@ -1287,12 +1285,12 @@ ENTRY(rfi_with_interrupt)
        movl r22=THIS_CPU(current_psr_i_addr)
        // set cr.ipsr (make sure cpl==2!)
        mov r29=r17
-       movl r28=DELIVER_PSR_SET;;
+       movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1)
+       movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
        mov r20=1;;
        ld8 r22=[r22]
-       movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0)
-       or r29=r29,r28;;
        and r29=r29,r27;;
+       or r29=r29,r28;;
        mov cr.ipsr=r29;;
        // v.ipsr and v.iip are already set (and v.iip validated) as rfi target
        // set shared_mem interrupt_delivery_enabled to 0
@@ -1935,7 +1933,7 @@ ENTRY(fast_insert)
        or r20=r20,r21 ;;       // r20==return value from lookup_domain_mpa
        // r16=pteval,r20=pteval2
        movl r19=_PAGE_PPN_MASK
-       movl r21=_PAGE_PL_2;;
+       movl r21=_PAGE_PL_PRIV;;
        andcm r25=r16,r19;;     // r25==pteval & ~_PAGE_PPN_MASK
        and r22=r20,r19;;
        or r22=r22,r21;;

diff --git a/xen/arch/ia64/xen/ivt.S b/xen/arch/ia64/xen/ivt.S
index ac4ad3d5b23b19a6573e0d442cfbba7fcf3eec24..1b1d8987de711608fd02fbb388df68f01a37a867 100644 (file)
--- a/xen/arch/ia64/xen/ivt.S
+++ b/xen/arch/ia64/xen/ivt.S
@@ -510,7 +510,8 @@ ENTRY(break_fault)
 (p7)   br.spnt.many dispatch_privop_fault
        ;;
 #endif
-       // if (ipsr.cpl == 2 && (iim - HYPERPRIVOP_START) < HYPERPRIVOP_MAX)
+       // if (ipsr.cpl == CONFIG_CPL0_EMUL &&
+       //    (iim - HYPERPRIVOP_START) < HYPERPRIVOP_MAX)
        // this is a hyperprivop. A hyperprivop is hand-coded assembly with
        // psr.ic off which means it can make no calls, cannot use r1-r15,
        // and it can have no memory accesses unless they are to pinned
@@ -524,7 +525,7 @@ ENTRY(break_fault)
        ;;
        cmp.gtu p7,p0=r21,r20
        ;;
-       cmp.eq.and p7,p0=2,r19                  // ipsr.cpl==2
+       cmp.eq.and p7,p0=CONFIG_CPL0_EMUL,r19   // ipsr.cpl==CONFIG_CPL0_EMUL
 (p7)   br.sptk.many fast_hyperprivop
        ;;
        movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
@@ -535,7 +536,7 @@ ENTRY(break_fault)
        ;;
        ld4 r23=[r23];;
        cmp4.eq p6,p0=r23,r17;;                 // Xen-reserved breakimm?
-       cmp.eq.and p6,p0=2,r19        
+       cmp.eq.and p6,p0=CONFIG_CPL0_EMUL,r19        
 (p6)   br.spnt.many fast_hypercall
        ;;
        br.sptk.many fast_break_reflect

diff --git a/xen/arch/ia64/xen/mm.c b/xen/arch/ia64/xen/mm.c
index efe519b1b981c8ffb1c6d9d253f0e3f0c1ce05bc..5e4ef77375079dfab2e683d15e1bceb4be028890 100644 (file)
--- a/xen/arch/ia64/xen/mm.c
+++ b/xen/arch/ia64/xen/mm.c
@@ -546,7 +546,7 @@ u64 translate_domain_pte(u64 pteval, u64 address, u64 itir__, u64* logps,
        /* Ignore non-addr bits of pteval2 and force PL0->2
           (PL3 is unaffected) */
        return (pteval & ~_PAGE_PPN_MASK) |
-              (pteval2 & _PAGE_PPN_MASK) | _PAGE_PL_2;
+              (pteval2 & _PAGE_PPN_MASK) | _PAGE_PL_PRIV;
 }
 
 // given a current domain metaphysical address, return the physical address
@@ -711,7 +711,8 @@ unsigned long lookup_domain_mpa(struct domain *d, unsigned long mpaddr,
         p2m_entry_set(entry, NULL, __pte(0));
     //XXX This is a work around until the emulation memory access to a region
     //    where memory or device are attached is implemented.
-    return pte_val(pfn_pte(0, __pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX)));
+    return pte_val(pfn_pte(0, __pgprot(__DIRTY_BITS | _PAGE_PL_PRIV |
+                                       _PAGE_AR_RWX)));
 }
 
 // FIXME: ONLY USE FOR DOMAIN PAGE_SIZE == PAGE_SIZE
@@ -785,7 +786,7 @@ __assign_new_domain_page(struct domain *d, unsigned long mpaddr,
     set_pte_rel(pte,
                 pfn_pte(maddr >> PAGE_SHIFT,
                         __pgprot(_PAGE_PGC_ALLOCATED | __DIRTY_BITS |
-                                 _PAGE_PL_2 | _PAGE_AR_RWX)));
+                                 _PAGE_PL_PRIV | _PAGE_AR_RWX)));
 
     smp_mb();
     return p;
@@ -820,7 +821,7 @@ assign_new_domain0_page(struct domain *d, unsigned long mpaddr)
 static unsigned long
 flags_to_prot (unsigned long flags)
 {
-    unsigned long res = _PAGE_PL_2 | __DIRTY_BITS;
+    unsigned long res = _PAGE_PL_PRIV | __DIRTY_BITS;
 
     res |= flags & ASSIGN_readonly ? _PAGE_AR_R: _PAGE_AR_RWX;
     res |= flags & ASSIGN_nocache ? _PAGE_MA_UC: _PAGE_MA_WB;

diff --git a/xen/arch/ia64/xen/oprofile/xenoprof.c b/xen/arch/ia64/xen/oprofile/xenoprof.c
index a1dd5128d4e5a9bbe9db0c9748c2869a438255a0..504d4f4fadfcb0869acbe3b23ab2bae515cd62e8 100644 (file)
--- a/xen/arch/ia64/xen/oprofile/xenoprof.c
+++ b/xen/arch/ia64/xen/oprofile/xenoprof.c
@@ -28,20 +28,26 @@
 int
 xenoprofile_get_mode(struct vcpu *v, struct cpu_user_regs * const regs)
 {
-    int mode = 0;
+    int mode;
 
     // mode
     // 0: user, 1: kernel, 2: xen
-    // Xen/IA64 uses ring2 for kernel, and doesn't use ring1.
-    if (ring_2(regs))
-        mode = 1;
-    else if (ring_0(regs))
-        mode = 2;
-    else if (ring_1(regs)) {
-        gdprintk(XENLOG_ERR, "%s:%d ring1 is used!\n", __func__, __LINE__);
-        mode = 1;// fall back to kernel mode.
+    switch (ring(regs))
+    {
+        case 3:
+                mode = 0;
+                break;
+        case CONFIG_CPL0_EMUL:
+                mode = 1;
+                break;
+        case 0:
+                mode = 2;
+                break;
+        default:
+                gdprintk(XENLOG_ERR, "%s:%d ring%d is used!\n", __func__,
+                         __LINE__, 3 - CONFIG_CPL0_EMUL);
+                mode = 1; /* fall back to kernel mode. */
     }
-
     return mode;
 }
 

diff --git a/xen/arch/ia64/xen/privop.c b/xen/arch/ia64/xen/privop.c
index 8ca6e49b8b75ce88f5ca6895b21355bd2913aae2..ba766783029f5c040ae30aa01522738593d5c9d4 100644 (file)
--- a/xen/arch/ia64/xen/privop.c
+++ b/xen/arch/ia64/xen/privop.c
@@ -636,7 +636,7 @@ static IA64FAULT priv_handle_op(VCPU * vcpu, REGS * regs, int privlvl)
        }
        if (slot_type == B && inst.generic.major == 0 && inst.B8.x6 == 0x0) {
                // break instr for privified cover
-       } else if (privlvl != 2)
+       } else if (privlvl > CONFIG_CPL0_EMUL)
                return IA64_ILLOP_FAULT;
        switch (slot_type) {
        case M:

diff --git a/xen/arch/ia64/xen/vcpu.c b/xen/arch/ia64/xen/vcpu.c
index d9925667d13e7e9f7ba6e8e84e78856e1c267478..43954de26925e05b25b456abed521ccc31352dd0 100644 (file)
--- a/xen/arch/ia64/xen/vcpu.c
+++ b/xen/arch/ia64/xen/vcpu.c
@@ -158,7 +158,7 @@ void vcpu_init_regs(struct vcpu *v)
                regs->cr_ipsr &= ~(IA64_PSR_BITS_TO_CLEAR
                                   | IA64_PSR_RI | IA64_PSR_IS);
                // domain runs at PL2
-               regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
+               regs->cr_ipsr = vcpu_pl_adjust(regs->cr_ipsr,IA64_PSR_CPL0_BIT);
                // lazy fp 
                PSCB(v, hpsr_dfh) = 1;
                PSCB(v, hpsr_mfh) = 0;
@@ -174,7 +174,7 @@ void vcpu_init_regs(struct vcpu *v)
                VCPU(v, dcr) = 0;
        } else {
                init_all_rr(v);
-               regs->ar_rsc |= (2 << 2);       /* force PL2/3 */
+               regs->ar_rsc = vcpu_pl_adjust(regs->ar_rsc, 2);
                VCPU(v, banknum) = 1;
                VCPU(v, metaphysical_mode) = 1;
                VCPU(v, interrupt_mask_addr) =
@@ -496,7 +496,7 @@ IA64FAULT vcpu_set_psr(VCPU * vcpu, u64 val)
        PSCB(vcpu, interrupt_collection_enabled) = vpsr.ic;
        vcpu_set_metaphysical_mode(vcpu, !(vpsr.dt && vpsr.rt && vpsr.it));
 
-       newpsr.cpl |= vpsr.cpl | 2;
+       newpsr.cpl |= max(vpsr.cpl, (u64)CONFIG_CPL0_EMUL);
 
        if (PSCB(vcpu, banknum) != vpsr.bn) {
                if (vpsr.bn)
@@ -535,10 +535,10 @@ u64 vcpu_get_psr(VCPU * vcpu)
        newpsr.ia64_psr.pp = PSCB(vcpu, vpsr_pp);
 
        /* Fool cpl.  */
-       if (ipsr.ia64_psr.cpl < 3)
+       if (ipsr.ia64_psr.cpl <= CONFIG_CPL0_EMUL)
                newpsr.ia64_psr.cpl = 0;
        else
-               newpsr.ia64_psr.cpl = 3;
+               newpsr.ia64_psr.cpl = ipsr.ia64_psr.cpl;
 
        newpsr.ia64_psr.bn = PSCB(vcpu, banknum);
        
@@ -1646,7 +1646,7 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u64 address, BOOLEAN is_data,
 
                } else {
                        *pteval = (address & _PAGE_PPN_MASK) |
-                               __DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX;
+                               __DIRTY_BITS | _PAGE_PL_PRIV | _PAGE_AR_RWX;
                        *itir = PAGE_SHIFT << 2;
                        perfc_incr(phys_translate);
                        return IA64_NO_FAULT;
@@ -1711,7 +1711,7 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u64 address, BOOLEAN is_data,
                REGS *regs = vcpu_regs(vcpu);
                // NOTE: This is specific code for linux kernel
                // We assume region 7 is identity mapped
-               if (region == 7 && ia64_psr(regs)->cpl == 2) {
+               if (region == 7 && ia64_psr(regs)->cpl == CONFIG_CPL0_EMUL) {
                        pte.val = address & _PAGE_PPN_MASK;
                        pte.val = pte.val | pgprot_val(PAGE_KERNEL);
                        goto out;
@@ -2090,8 +2090,8 @@ vcpu_set_tr_entry_rid(TR_ENTRY * trp, u64 pte,
        trp->rid = rid;
        ps = trp->ps;
        new_pte.val = pte;
-       if (new_pte.pl < 2)
-               new_pte.pl = 2;
+       if (new_pte.pl < CONFIG_CPL0_EMUL)
+               new_pte.pl = CONFIG_CPL0_EMUL;
        trp->vadr = ifa & ~0xfff;
        if (ps > 12) {          // "ignore" relevant low-order bits
                new_pte.ppn &= ~((1UL << (ps - 12)) - 1);

diff --git a/xen/arch/ia64/xen/xenasm.S b/xen/arch/ia64/xen/xenasm.S
index bbc88f8ea06c732e5fcf57211a3c299429f64908..c4fe3cd65b1664a0672f83dca9cad065028a36b3 100644 (file)
--- a/xen/arch/ia64/xen/xenasm.S
+++ b/xen/arch/ia64/xen/xenasm.S
@@ -11,6 +11,7 @@
 #include <asm/pgtable.h>
 #include <asm/vhpt.h>
 #include <asm/asm-xsi-offsets.h>
+#include <asm/vmmu.h>
 #include <public/xen.h>
        
 // Change rr7 to the passed value while ensuring
@@ -148,7 +149,7 @@ GLOBAL_ENTRY(ia64_new_rr7)
 
        //  Shared info
        mov r24=XSI_SHIFT<<2
-       movl r25=__pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RW)
+       movl r25=__pgprot(__DIRTY_BITS | _PAGE_PL_PRIV | _PAGE_AR_RW)
        ;;
        ptr.d   in3,r24
        or r23=in1,r25                  // construct PA | page properties

diff --git a/xen/include/asm-ia64/config.h b/xen/include/asm-ia64/config.h
index f94c23cbbaff9c805381a11000efd5011e7eb3c7..0c499f6353c7f9bdf7cdecb252445601a8067079 100644 (file)
--- a/xen/include/asm-ia64/config.h
+++ b/xen/include/asm-ia64/config.h
@@ -55,6 +55,9 @@
 
 #define NR_hypercalls 64
 
+/* PV domains use this value for priv. level 0 emulation */
+#define CONFIG_CPL0_EMUL       1
+
 #ifndef __ASSEMBLY__
 
 // can't find where this typedef was before?!?

diff --git a/xen/include/asm-ia64/linux-xen/asm/ptrace.h b/xen/include/asm-ia64/linux-xen/asm/ptrace.h
index d38f4e93909d2e06aea80cb3cf9a59a00d1a1d2c..8bcdf96442ffd1b0a89b15fe32193b82e0bbd0f4 100644 (file)
--- a/xen/include/asm-ia64/linux-xen/asm/ptrace.h
+++ b/xen/include/asm-ia64/linux-xen/asm/ptrace.h
@@ -267,7 +267,7 @@ struct switch_stack {
 # define ia64_psr(regs)                        ((struct ia64_psr *) &(regs)->cr_ipsr)
 #ifdef XEN
 # define guest_mode(regs)              (ia64_psr(regs)->cpl != 0)
-# define guest_kernel_mode(regs)       (ia64_psr(regs)->cpl == 2)
+# define guest_kernel_mode(regs)       (ia64_psr(regs)->cpl == CONFIG_CPL0_EMUL)
 #else
 # define user_mode(regs)               (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0)
 #endif

diff --git a/xen/include/asm-ia64/vcpu.h b/xen/include/asm-ia64/vcpu.h
index 448b8a8a290721e011dbbbe3f8676c34e0115aa3..2e3f6bd9792774378d858c8fef021b34c6335e20 100644 (file)
--- a/xen/include/asm-ia64/vcpu.h
+++ b/xen/include/asm-ia64/vcpu.h
@@ -203,6 +203,16 @@ static inline s64 vcpu_get_next_timer_ns(VCPU * vcpu)
        return vcpu_get_next_timer_ns;
 }
 
+static inline u64 vcpu_pl_adjust(u64 reg, u64 shift)
+{
+       u64 pl;
+
+       pl = reg & (3UL << shift);
+       if (pl < ((u64)CONFIG_CPL0_EMUL << shift))
+               pl = (u64)CONFIG_CPL0_EMUL << shift;
+       return (reg & ~(3UL << shift)) | pl;
+}
+
 #define verbose(a...) do {if (vcpu_verbose) printk(a);} while(0)
 
 //#define vcpu_quick_region_check(_tr_regions,_ifa) 1

diff --git a/xen/include/asm-ia64/vmmu.h b/xen/include/asm-ia64/vmmu.h
index 39f04c6eb9befbb00364167e4510b9e007384c62..668a0ceb9674cc03f28ebd2ca010d1004948419f 100644 (file)
--- a/xen/include/asm-ia64/vmmu.h
+++ b/xen/include/asm-ia64/vmmu.h
@@ -32,6 +32,7 @@
 #define     VCPU_VHPT_ORDER     (VCPU_VHPT_SHIFT - PAGE_SHIFT)
 #define     VTLB(v,_x)          (v->arch.vtlb._x)
 #define     VHPT(v,_x)          (v->arch.vhpt._x)
+#define     _PAGE_PL_PRIV       (CONFIG_CPL0_EMUL << 7)
 #ifndef __ASSEMBLY__
 
 #include <xen/config.h>